Fujitsu MB86R02 Jade-D Hardware Manual page 282

MB86R02 'Jade-D' Hardware Manual V1.64
External trigger
DREQ
DACK
DEOP
DSTP
Software trigger
DMACA[31:24] 0x00
HBUSREQ
HGRANT
HCLK
HMASTER CPU
HTRANS
HADDR
HWRITE
Control
HWDATA
HRDATA
HREADY
HRESP
DMACA[19:16] 0x0
BC
DMACA[15:0] 0x0
TC
DMACSA
DMACDA
0xA0
HDMAC
N N N
DA SA DA
SA
Data
Data
0x1
0x1
SA0
DA0
Figure 15-3 Block transfer (for BC = 0x1 and TC = 0x1)
Break of transfer
CPU
N I N N
SA
Data
Data
OK
0x0
SA1 SA2
DA1 DA2
0x00
HDMAC CPU
N N I
DA SA DA
Data
Data
Data Data
0x1 0x0
0x0
SA3 SA4
DA3 DA4
15-19