Table of Contents
Advertisement
MB86R02 'Jade-D' Hardware Manual V1.64
11.6.4
Memory controller error register (MCERR) ................................................................. 11-11
11.7
Connection example ....................................................................................................... 11-12
11.8
Example of access waveform ......................................................................................... 11-13
11.9
Operation ........................................................................................................................ 11-17
11.9.1
External bus interface ................................................................................................. 11-17
11.9.2
Low-speed device interface function .......................................................................... 11-17
11.9.3
Endian and byte lane to each access ......................................................................... 11-18
12
Embedded SRAM .................................................................................................................... 12-1
12.1
Outline .............................................................................................................................. 12-1
12.2
Features ........................................................................................................................... 12-1
12.3
Block diagram ................................................................................................................... 12-1
12.4
Supply clock ..................................................................................................................... 12-1
13
DDR2 Controller ...................................................................................................................... 13-1
13.1
Outline .............................................................................................................................. 13-1
13.2
Features ........................................................................................................................... 13-1
13.3
Limitation .......................................................................................................................... 13-1
13.4
Block Diagram .................................................................................................................. 13-2
13.5
Supply Clock ..................................................................................................................... 13-3
13.6
Registers .......................................................................................................................... 13-3
13.6.1
Register List .................................................................................................................. 13-3
13.6.2
DRAM initialization control register (DRIC) .................................................................. 13-5
13.6.3
DRAM initialization command register [1] (DRIC1) ...................................................... 13-7
13.6.4
DRAM initialization command register [2] (DRIC2) ...................................................... 13-7
13.6.5
DRAM CTRL ADD register (DRCA).............................................................................. 13-8
13.6.6
DRAM control mode register (DRCM) .......................................................................... 13-9
13.6.7
DRAM CTRL SET TIME1 Register (DRCST1) ........................................................... 13-10
13.6.8
DRAM CTRL SET TIME2 register (DRCST2) ............................................................ 13-12
13.6.9
DRAM CTRL REFRESH register (DRCR) .................................................................. 13-14
13.6.10
DRAM CTRL FIFO register (DRCF)........................................................................ 13-15
13.6.11
AXI setting register (DRASR) .................................................................................. 13-16
13.6.12
DRAM IF MACRO SETTING DLL register (DRIMSD) ............................................ 13-17
13.6.13
DRAM ODT SETTING register (DROS) ................................................................. 13-18
13.6.14
IO buffer setting ODT1 (DRIBSODT1) .................................................................... 13-19
13.6.15
IO buffer setting OCD (DRIBSOCD) ....................................................................... 13-20
13.6.16
IO buffer setting OCD2 (DRIBSOCD2) ................................................................... 13-21
13.6.17
ODT auto bias adjust register (DROABA) ............................................................... 13-22
13.6.18
ODT bias select register (DROBS) ......................................................................... 13-23
13.6.19
IO monitor register 1 (DRIMR1) .............................................................................. 13-24
13.6.20
IO monitor register 2 (DRIMR2) .............................................................................. 13-24
13.6.21
IO monitor register 3 (DRIMR3) .............................................................................. 13-25
13.6.22
IO monitor register 4 (DRIMR4) .............................................................................. 13-25
13.6.23
OCD impedance setting register 1 (DROISR1) ...................................................... 13-26
13.6.24
OCD impedance setting register 2 (DROISR2) ...................................................... 13-26
13.7
Operation ........................................................................................................................ 13-27
13.7.1
DRAM Initialization Sequence .................................................................................... 13-27
13.7.2
DRAM Initialization Procedure .................................................................................... 13-28
13.7.2.1
SDRAM Initialization Procedure .......................................................................... 13-30
13.7.2.2
OCD Adjustment Procedure ................................................................................ 13-33
13.7.2.3
ODT Setting Procedure ....................................................................................... 13-35
14
Timer (TIMER) ......................................................................................................................... 14-1
14.1
Outline .............................................................................................................................. 14-1
14.2
Feature ............................................................................................................................. 14-1
Advertisement
Table of Contents
