MB86R02 'Jade-D' Hardware Manual V1.64
6.4 Processing Mode
6.4.1 Parameter setting for 666MHz PLL clock
• All register values in the following tables are valid for PLL clock = 666MHz
6.4.1.1 Parameter setting for SSCG-speed of 15KHz
Given:
SSCG_ FREQUENCY_OFFSET = 0 (default),
SSCG_PEAK_FREQUENCY = 0 (default)
SSCG_PERIOD_JITTER = 10 % (default)
SSCG_TYPE
3
Center Spread
2
Upspread
1
Downspread
Table 6-3 SSCG speed of 15KHz (refer to 666MHz PLL clock)
6-8
SSCG_PERIOD
PERIOD_DELTA
0xAC
0xAC
0xAC
Modulation Peak %
0.5
1.0
1.5
0x8A
2.0
2.5
3.0
0.5
1.0
1.5
0x8A
2.0
2.5
3.0
0.5
1.0
1.5
0x8A
2.0
2.5
3.0
SSCG_STEP
0x6ED0
0xDDA0
0x1 4C70
0x1 BB40
0x2 2A10
0x2 9820
0x3768
0x6ED0
0xA638
0xDDA0
0x1 1508
0x1 4C70
0x3768
0x6ED0
0xA638
0xDDA0
0x1 1508
0x1 4C70