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MB86R02 'Jade-D' Hardware Manual V1.64
13.6.12
DRAM IF MACRO SETTING DLL register (DRIMSD)
This register is for DDR2-SDRAM interface macro setting which drives macro pin corresponding
to each bit by the setting value. This is also for DLL timing setting.
Address
Bit
15
14
13
Name
-
ISFT_3[2:0]
R/W
R/W
R/W
Initial value
X
1
1
Bit field
No.
Name
15
(Reserved)
14-12
ISFT_3[2:0]
11
(Reserved)
10-8
ISFT_2[2:0]
7
(Reserved)
6-4
ISFT_1[2:0]
3
(Reserved)
2-0
ISFT_0[2:0]
F300_0000H + 50H
12
11
10
9
-
ISFT_2[2:0]
R/W
R/W
0
X
1
1
Reserved bit.
Write access is ignored.
Value of ISFT_3[2:0]
110
(Initial value)
101
Normal operation setting value (set to 101 at DRAM initialization)
Others Reserved (setting prohibited)
Reserved bit.
Write access is ignored.
Value of ISFT_2[2:0]
110
(Initial value)
101
Normal operation setting value (set to 101 at DRAM initialization)
Others Reserved (setting prohibited)
Reserved bit.
Write access is ignored.
Value of ISFT_1[2:0]
110
(Initial value)
101
Normal operation setting value (set to 101 at DRAM initialization)
Others Reserved (setting prohibited)
Reserved bit.
Write access is ignored.
Value of ISFT_0[2:0]
110
(Initial value)
101
Normal operation setting value (set to 101 at DRAM initialization)
Others Reserved (setting prohibited)
8
7
6
5
-
ISFT_1[2:0]
R/W
R/W
0
X
1
1
Description
4
3
2
1
-
ISFT_0[2:0]
R/W
R/W
0
X
1
1
13-17
0
0
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