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MB86R02 'Jade-D' Hardware Manual V1.64
IMASK (Interrupt MASK)
Register
HostBaseAddress + 24
address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit field name
R/W
Initial value
*1 Reserved
This register masks interrupt requests. Even when the interrupt request is issued for the bit to
which "0" is written, interrupt signal is not asserted for CPU.
Bit 0
CERRM (Command Error Interrupt Mask)
Masks drawing command execution error interrupt
Bit 1
CENDM (Command Interrupt Mask)
Masks drawing command end interrupt
Bit 2
VSYNC0M (Vertical Sync. of display 0 Interrupt Mask)
Masks vertical synchronization interrupt
Bit 3
FSYNC0H (Frame Sync. of display 0 Interrupt Mask)
Masks frame synchronization interrupt
Bit 4
SYNCERR0M (Sync Error of display 0 Mask)
Masks external synchronization error interrupt
Bit 5
REGUD0M (Register update of display 0 Mask)
Masks register update interrupt
Bit 6
VSYNC1M (Vertical Sync. of display 1 Interrupt Mask)
Masks vertical synchronization interrupt
Bit 7
FSYNC1H (Frame Sync. of display 1 Interrupt Mask)
Masks frame synchronization interrupt
Bit 8
SYNCERR1M (Sync Error of display 1 Mask)
Masks external synchronization error interrupt
Bit 9
REGUD1M (Register update of display 1 Mask)
Masks register update interrupt
Bit 10
CAP0M (Capture 0 Mask)
Masks video capture 0 interrupt
Bit 11
CAP1M (Capture 1 Mask)
Masks video capture 1 interrupt
H
Reserved
Resv
R0
R0W0
0
Reserved
R0
0
0
IMASK
RW
0
18-251
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