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MB86R02 'Jade-D' Hardware Manual V1.64
9.5.7 Delay interrupt control register (DICR)
The DICR register controls the delay interrupt for the task switch.
The IRQ interrupt request can be issued, and software be cancelled by the writing operation to this
register.
The delay interrupt is allocated in IRQ30 of IRC0.
Address
FFFF_FE00
Bit
31
30
29
Name
-
-
-
R/W
R/W
R/W
R/W
Initial value
X
X
X
Bit
15
14
13
Name
-
-
-
R/W
R/W
R/W
R/W
Initial value
X
X
X
Bit field
Number
Name
31-1
-
0
DLYI
9-20
IRC0:
or FFFE_8000
+ 14
H
H
H
28
27
26
25
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
12
11
10
9
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
It is an unused bit.
The write access is ignored. The read value of these bits is undefined.
The delay interrupt is controlled.
Write "0" to this bit to cancel the delay interrupt.
0 The delay interrupt factor is cancelled. The interrupt request doesn't occur.
1 The delay interrupt factor is generated. The interrupt request occurs.
This bit is initialized by reset by "0".
IRC1: FFFB_0000
IRC2: FFFB_1000
24
23
22
21
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
8
7
6
5
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
Explanation
+ 14
H
H
+ 14
H
H
20
19
18
17
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
4
3
2
1
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
16
-
R/W
X
0
DLYI
R/W
0
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