Fujitsu MB86R02 Jade-D Hardware Manual page 189

MB86R02 'Jade-D' Hardware Manual V1.64
9.5.8 Table base register (TBR)
The TBR register shows the upper address of the IRQ vector (24 bits). When the interrupt controller
receives the IRQ interrupt source, and IRQ is asserted to the ARM core, the address displayed in the
VCT register is as follows.
(Set value of TBR register) + Individual IRQ interrupt source vector address
Address
FFFF_FE00
Bit 31 30 29
Name TBR31 TBR30 TBR29 TBR28 TBR27 TBR26 TBR25 TBR24 TBR23 TBR22 TBR21 TBR20 TBR19 TBR18 TBR17 TBR16
R/W R/W R/W R/W
Initial value 0 0 0
Bit 15 14 13
Name TBR15 TBR14 TBR13 TBR12 TBR11 TBR10 TBR9
R/W R/W R/W R/W
Initial value 0 0 0
Bit field
Number Name
31-8 TBR31-8
7-0 Zero
IRC0:
or FFFE_8000 + 1C
H H H
28 27 26 25
R/W R/W R/W R/W
0 0 0 0
12 11 10 9
R/W R/W R/W R/W
0 0 0 0
Set the upper address of the IRQ vector (24 bits).
These bits are initialized by reset by "0".
These bits are the "0" fixation.
Writing is invalid. "0" can be read in the read value of these bits at any time.
These bits are initialized by reset by "0".
IRC1: FFFB_0000
IRC2: FFFB_1000
24 23 22 21
R/W R/W R/W R/W
0 0 0 0
8 7 6 5
TBR8 Zero Zero Zero
R/W R R R
0 0 0 0
Explanation
+ 1C
H H
+ 1C
H H
20 19 18 17
R/W R/W R/W R/W
0 0 0 0
4 3 2 1
Zero Zero Zero Zero
R R R R
0 0 0 0
16
R/W
0
0
Zero
R
0
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