Supply Clock; Limitations - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

Figure 24-2 Block diagram of a GPIO module and RSDS-TTL IO cell

Note on configuration:

GPIOs must be configured in Input and Output direction pairs when the fourth multiplex function

of DISP0 is selected. Pairs are (DISP0P,DISP0N), (DISP1P,DISP1N)...(DISP11P,DISP11N).

24.4 Supply clock

The APB clock is supplied to the GPIO module. Please refer to "5. Clock reset generator (CRG)"

for the frequency setting and control specifications of the APB clock.

If GPIO functionality is mapped to pins DISPxP/N (see MPXTABLE3, chapter "1.6.1 Pin

Multiplex"), then direction control can only be applied pairwise for P and N pins together. That

means, only the data direction control registers of GPIO ports with even number are active.