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MB86R02 'Jade-D' Hardware Manual V1.64
27.6.11
I2SxINTCNT register ............................................................................................... 27-16
27.6.12
I2SxSTATUS register .............................................................................................. 27-19
27.6.13
I2SxDMAACT register ............................................................................................. 27-21
27.7
Operation ........................................................................................................................ 27-22
27.7.1
Outline ......................................................................................................................... 27-22
27.7.2
Transfer start, stop, and malfunction .......................................................................... 27-23
27.7.3
Frame construction ..................................................................................................... 27-29
27.7.3.1
1 sub frame construction ..................................................................................... 27-29
27.7.3.2
2 sub frame construction ..................................................................................... 27-30
27.7.3.3
Bit alignment ........................................................................................................ 27-31
27.7.4
FIFO construction and description .............................................................................. 27-33
28
UART Interface ........................................................................................................................ 28-1
28.1
Outline .............................................................................................................................. 28-1
28.2
Feature ............................................................................................................................. 28-1
28.3
Block diagram ................................................................................................................... 28-1
28.4
Related pin ....................................................................................................................... 28-2
28.5
Supply clock ..................................................................................................................... 28-2
28.6
Registers .......................................................................................................................... 28-3
28.6.1
Register list ................................................................................................................... 28-3
28.6.2
Reception FIFO register (URTxRFR) ........................................................................... 28-6
28.6.3
Transmission FIFO register (URTxTFR) ...................................................................... 28-6
28.6.4
Interrupt enable register (URTxIER) ............................................................................. 28-7
28.6.5
Interrupt ID register (URTxIIR) ...................................................................................... 28-8
28.6.6
FIFO control register (URTxFCR) ................................................................................. 28-9
28.6.7
Line control register (URTxLCR) ................................................................................ 28-10
28.6.8
Modem control register (URTxMCR) .......................................................................... 28-11
28.6.9
Line status register (URTxLSR) .................................................................................. 28-12
28.6.10
Modem status register (URTxMSR) ........................................................................ 28-13
28.6.11
Divider latch register (URTxDLL&URTxDLM) ......................................................... 28-14
28.7
UART operation .............................................................................................................. 28-16
28.7.1
Example of initial setting ............................................................................................. 28-16
28.7.2
Example of transfer procedure ................................................................................... 28-17
28.7.3
Example of reception procedure ................................................................................. 28-18
28.7.4
Basic transmission operation ...................................................................................... 28-19
28.7.5
Basic reception operation ........................................................................................... 28-20
28.7.6
Line status ................................................................................................................... 28-21
28.7.7
Character time-out interrupt ........................................................................................ 28-25
29
I2C Bus Interface ..................................................................................................................... 29-1
29.1
Outline .............................................................................................................................. 29-1
29.2
Features ........................................................................................................................... 29-1
29.3
Block diagram ................................................................................................................... 29-2
29.4
Block functions ................................................................................................................. 29-3
29.5
Related pins ...................................................................................................................... 29-4
29.6
Supply clock ..................................................................................................................... 29-4
29.7
Register ............................................................................................................................ 29-5
29.7.1
Register list ................................................................................................................... 29-5
29.7.2
Bus status register (I2CxBSR) ...................................................................................... 29-7
29.7.3
Bus control register (I2CxBCR) .................................................................................... 29-9
29.7.4
Clock control register (I2CxCCR) ............................................................................... 29-12
29.7.5
Address register (I2CxADR) ....................................................................................... 29-15
29.7.6
Data register (I2CxDAR) ............................................................................................. 29-16
29.7.7
Two bus control registers (I2CxBC2R) ....................................................................... 29-17
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