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ColdFire Core
The acceleration logic uses a static prediction algorithm when processing conditional branch (Bcc)
instructions. The default prediction scheme is as follows: forward Bcc instructions are predicted as not
taken, while backward Bcc opcodes are predicted as taken. A user-mode bit in the condition control
register, CCR[P], supports altering the prediction dynamically for forward Bcc instructions. See
Section 3.2.4, "Condition Code Register
Depending on the run-time characteristics of an application, processor performance may be increased
significantly by setting or clearing this configuration bit.
Times," gives details on individual instruction performance.
Memory Map/Register Description
3.2
The following sections describe the processor registers in the user and supervisor programming models.
The programming model is selected based on the processor privilege level (user mode or supervisor mode)
as defined by the S bit of the status register (SR).
The user-programming model consists of the following registers:
•
16 general-purpose 32-bit registers (D0–D7, A0–A7)
•
32-bit program counter (PC)
•
8-bit condition code register (CCR)
•
EMAC registers
— Four 48-bit accumulator registers partitioned as follows:
– Four 32-bit accumulators (ACC0–ACC3)
– Eight 8-bit accumulator extension bytes (two per accumulator). These are grouped into two
32-bit values for load and store operations (ACCEXT01 and ACCEXT23).
Accumulators and extension bytes can be loaded, copied, and stored, and results from EMAC
arithmetic operations generally affect the entire 48-bit destination.
— One 16-bit mask register (MASK)
— One 32-bit Status register (MACSR) including four indicator bits signaling product or
accumulation overflow (one for each accumulator: PAV0–PAV3)
The supervisor programming model is to be used only by system control software to implement restricted
operating system functions, I/O control, and memory management. All accesses that affect the control
features of ColdFire processors are in the supervisor programming model, which consists of registers
available in user mode as well as the following control registers:
•
16-bit status register (SR)
•
32-bit supervisor stack pointer (SSP)
•
32-bit vector base register (VBR)
•
32-bit cache control register (CACR)
•
32-bit access control registers (ACR0, ACR1)
•
One 32-bit memory base address register (RAMBAR)
3-4
(CCR)."
(described fully in
Chapter 4, "Enhanced Multiply-Accumulate Unit (EMAC
MCF5329 Reference Manual, Rev 3
Section 3.3.5.7, "Branch Instruction Execution
Table 3-1
lists the processor registers.
:
Freescale Semiconductor
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