Multi-Core Jtag And Oce Module Concept - Freescale Semiconductor MSC8144E Reference Manual

25.1.4 Multi-Core JTAG and OCE Module Concept

The MSC8144E uses JTAG TAP for standard defined testing compatibilities and for multi-core
OCE module control and OCE module interconnection control. The MSC8144E has four internal
OCE modules, one module per SC3400 core. The OCE modules interconnect in a chain and are
configured and directed by the JTAG TAP controller. Figure 25-4 shows the chained connection.
sjt_tdi
OCE
Command
choose_tdi
Register
Figure 25-4. JTAG TAP Controller and OCE Module Multi-Core Interconnection
Each of the four MSC8144E OCE modules has an interface to a JTAG port. The interface is
active even when a reset signal to the SC3400 core is asserted. However, system reset must be
deasserted to allow a proper interface with the cores. This interface is synchronized with the
internal clocks derived from the JTAG
an event counter, an event detector unit, a synchronizer, an event selector, and a trace unit.
Note: For details on the OCE module features, consult the OCE Architecture Manual.
The JTAG port performs the following tasks via the JTAG-OCE module interface:
Chooses one or more OCE module blocks (CHOOSE_ONCE)
Issues a debug request to the OCE module (DEBUG_REQUEST)
Writes an OCE command to the OCE Command Register (DEBUG_REQUEST or
ENABLE_ONCE)
Reads and writes to internal OCE registers (DEBUG_REQUEST or ENABLE_ONCE)
Queries the status of the OCE block (RD_STATUS)
Freescale Semiconductor
OCE
Command
Register
choose_clock_dr
ext_trst_n
tck_clk
JTAG TAP Controller
clock. Each OCE module includes an OCE controller,
TCK
MSC8144E Reference Manual, Rev. 3
TAP, Boundary Scan, and OCE
OCE OCE
Command Command
Register Register
oce_tdo
25-9