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Table 12-4. Supported DDR2 Device Configurations
SDRAM Device
Device Configuration
256 Mb
256 Mb
512 Mb
512 Mb
1 Gb
1 Gb
2 Gb
128Mb × 16
2 Gb
4 Gb
256Mb × 16
4 Gb
If a transaction request is issued to the DDR memory controller and the address does not lie
within any of the programmed address ranges for an enabled chip select, a memory select error is
flagged (see Section 12.5, Error Management, on page 12-24).
If the starting and ending address of a disabled bank overlaps with the address space of an
enabled bank, system memory in the overlapping address range may be corrupted. The starting
and ending addresses of unused memory banks should be mapped to unused memory space.
Using a memory-polling algorithm at power-on reset, system firmware configures the
memory-boundary registers to map the size of each bank in memory. The memory controller uses
its bank map to assert the appropriate
starting and ending addresses. The memory banks do not have to be mapped to a contiguous
address space.
12.1.3
DDR SDRAM Address Multiplexing
Table 12-5 and Table 12-6 show the address bit encodings for each DDR SDRAM
configuration. The address at the memory controller signals
as the LSB. Also,
MA0
so the column address can never use
Freescale Semiconductor
Row × Column ×
Sub-bank Bits
32 Mb × 8
13 × 10 × 2
16 Mb × 16
13 × 9 × 2
64 Mb × 8
14 × 10 × 2
32 Mb × 16
13 × 10 × 2
128 Mb × 8
14 × 10 × 3
64 Mb × 16
13 × 10 × 3
256 Mb × 8
15 × 10 × 3
14 × 10 × 3
512 Mb × 8
16 × 10 × 3
15 × 10 × 3
signal for memory accesses according to the bank
MCSx
is the auto-precharge bit in DDR1/DDR2 modes for reads and writes,
MA10
.
MA10
MSC8144E Reference Manual, Rev. 3
32-Bit Bank Size
Two Banks of Memory
128 MB
64 MB
256 MB
128 MB
512 MB
256 MB
1 GB
512 MB
2 GB
1 GB
use
as the MSB and
MA[15–0]
MA15
Architecture
256 MB
128 MB
512 MB
256 MB
1 GB
512 MB
2 GB
1 GB
4 GB
2 GB
12-7
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