ST STM32F413VG Cortex-M4 Microcontroller Manuals
Manuals and User Guides for ST STM32F413VG Cortex-M4 Microcontroller. We have 1 ST STM32F413VG Cortex-M4 Microcontroller manual available for free PDF download: Reference Manual
ST STM32F413VG Reference Manual (1324 pages)
advanced Arm-based 32-bit MCUs
Brand: ST
|
Category: Microcontrollers
|
Size: 15 MB
Table of Contents
-
Glossary53
-
I-Bus55
-
D-Bus55
-
S-Bus55
-
Busmatrix56
-
Introduction57
-
Bit Banding62
-
Introduction66
-
Erase72
-
Programming73
-
Interrupts74
-
Option Bytes74
-
Low-Power Modes100
-
Sleep Mode103
-
Stop Mode105
-
Standby Mode108
-
PWR Register Map116
-
Reset117
-
System Reset117
-
Power Reset118
-
Clocks119
-
HSE Clock121
-
HSI Clock122
-
LSE Clock123
-
LSI Clock124
-
RTC/AWU Clock125
-
Watchdog Clock125
-
RCC Registers129
-
For Stm32F413Xx140
-
For Stm32F423Xx141
-
For Stm32F413Xx151
-
For Stm32F423Xx152
-
RCC Register Map181
-
Port Pins194
-
GPIO Registers196
-
(X = a196
-
(X = a197
-
(X = a199
-
(X = a201
-
SYSCFG Registers204
-
(Syscfg_Exticr1)206
-
(Syscfg_Exticr2)206
-
(Syscfg_Exticr3)207
-
(Syscfg_Exticr4)208
-
DMA Introduction214
-
DMA Overview216
-
DMA Transactions217
-
Arbiter219
-
DMA Streams219
-
Circular Mode223
-
Fifo226
-
Flow Controller230
-
Error Management233
-
DMA Interrupts234
-
DMA Registers235
-
DMA Register Map245
-
NVIC Features249
-
EXTI Registers258
-
AHB Interface266
-
Introduction307
-
QUADSPI Pins308
-
QUADSPI Usage317
-
Ncs Behavior320
-
ADC Introduction336
-
ADC Clock338
-
Timing Diagram340
-
Analog Watchdog340
-
Scan Mode341
-
Data Alignment343
-
Data Management347
-
Using the DMA347
-
ADC Interrupts350
-
ADC Registers351
-
DAC Introduction366
-
DAC Data Format368
-
DAC Conversion369
-
DMA Request371
-
Noise Generation371
-
DAC Registers378
-
(Dac_Dhr12L1)382
-
(Dac_Dhr12L2)383
-
(Dac_Dhr12Ld)384
-
(Dac_Dhr8Rd)385
-
DAC Register Map386
-
Introduction388
-
Integrator Unit411
-
Analog Watchdog411
-
Extreme Detector414
-
Data Unit Block415
-
DFSDM Interrupts418
-
(Dfsdm_Fltxawsr)437
-
Introduction450
-
RNG Operation454
-
RNG Clocking455
-
Error Management455
-
RNG Interrupts456
-
Introduction457
-
Data Collection457
-
RNG Registers458
-
RNG Register Map461
-
Time-Base Unit464
-
Counter Modes466
-
Clock Selection478
-
PWM Input Mode485
-
PWM Mode487
-
One-Pulse Mode497
-
Debug Mode506
-
Time-Base Unit535
-
Counter Modes537
-
Clock Selection546
-
PWM Input Mode552
-
PWM Mode555
-
One-Pulse Mode558
-
Debug Mode571
-
Time-Base Unit598
-
Counter Modes600
-
Clock Selection603
-
PWM Mode610
-
One-Pulse Mode611
-
Debug Mode616
-
(Timx_Ccmr1)634
-
(Timx_Ccer)637
-
Introduction642
-
Time-Base Unit643
-
Counting Mode645
-
Clock Source648
-
Debug Mode649
-
TIM6/7 Registers650
-
Introduction655
-
Glitch Filter657
-
Prescaler658
-
Operating Mode659
-
Timeout Function661
-
Register Update662
-
Counter Mode663
-
Timer Enable663
-
Encoder Mode664
-
Debug Mode665
-
LPTIM Interrupts665
-
LPTIM Registers666
-
Debug Mode679
-
IWDG Registers680
-
Debug Mode687
-
WWDG Registers688
-
Introduction691
-
AES Interrupts729
-
AES Registers731
-
AES Register Map742
-
Introduction744
-
Tamper Detection756
-
Alarm Output758
-
RTC Interrupts759
-
RTC Registers760
-
(Rtc_Tafcr)775
-
RTC Register Map779
-
Introduction782
-
Mode Selection785
-
Software Reset790
-
Data Transfer791
-
Smbus Slave Mode820
-
Error Conditions827
-
DMA Requests829
-
Debug Mode830
-
FMPI2C Registers831
-
Mode Selection850
-
I2C Slave Mode851
-
I2C Master Mode854
-
Error Conditions860
-
Smbus862
-
DMA Requests865
-
I 2 C Interrupts867
-
I 2 C Debug Mode869
-
I 2 C Registers869
-
I2C Register Map882
-
Transmitter889
-
Receiver892
-
Parity Control909
-
Smartcard915
-
USART Interrupts923
-
USART Registers924
-
Introduction935
-
I2S Features937
-
SPI Status Flags953
-
SPI Error Flags954
-
TI Mode955
-
CRC Calculation956
-
SPI Interrupts958
-
Figure 330. I959
-
I2S Full-Duplex960
-
Figure 336. I963
-
Clock Generator967
-
I 2 S Slave Mode972
-
I 2 S Interrupts975
-
DMA Features975
-
Table 177. I975
-
Mode981
-
SPI Register Map986
-
Introduction987
-
Main Features988
-
Main SAI Modes990
-
Audio Data Size991
-
Frame Length992
-
FS Signal Role993
-
Internal Fifos997
-
Specific Features1000
-
Mute Mode1001
-
MONO/STEREO Function1001
-
Companding Mode1002
-
Error Flags1005
-
Interrupt Sources1008
-
Disabling the SAI1009
-
SAI DMA Interface1010
-
SAI Registers1011
-
SAI Register Map1024
-
SDIO Main Features1026
-
SDIO Bus Topology1026
-
SDIO Adapter1030
-
SDIO APB2 Interface1041
-
Card Reset1043
-
Block Write1044
-
Block Read1045
-
Card Status Register1051
-
SD Status Register1054
-
Table 192. SD Status1054
-
SD I/O Mode1058
-
Response Formats1062
-
Table 204. Lock Card1062
-
R1B1063
-
R3 (OCR Register)1064
-
R4 (Fast I/O)1064
-
R4B1064
-
SDIO Interrupts1067
-
HW Flow Control1067
-
SDIO Registers1068
-
SDIO Response 11071
-
SDIO Register Map1083
-
Introduction1085
-
Bxcan Main Features1085
-
CAN 2.0B Active Core1086
-
Tx Mailboxes1087
-
Acceptance Filters1087
-
Initialization Mode1089
-
Normal Mode1090
-
Test Mode1091
-
Silent Mode1091
-
Loop Back Mode1092
-
Reception Handling1095
-
Identifier Filtering1096
-
Message Storage1100
-
Error Management1102
-
Bit Timing1102
-
Bxcan Interrupts1105
-
CAN Registers1106
-
CAN Filter Registers1123
-
Bxcan Register Map1127
-
Introduction1131
-
OTG Main Features1132
-
General Features1132
-
Host-Mode Features1133
-
Split Rail for USB1133
-
OTG Implementation1134
-
OTG Block Diagram1135
-
OTG Core1136
-
Full-Speed OTG PHY1136
-
ID Line Detection1137
-
HNP Dual Role Device1138
-
SRP Dual Role Device1138
-
USB Peripheral1138
-
Peripheral States1139
-
Peripheral Endpoints1140
-
USB Host1142
-
SRP-Capable Host1143
-
USB Host States1143
-
Host Channels1145
-
Host Scheduler1146
-
SOF Trigger1147
-
Host Sofs1147
-
Peripheral Sofs1147
-
OTG Low-Power Modes1148
-
USB Data Fifos1149
-
FIFO RAM Allocation1152
-
OTG_FS Interrupts1154
-
CSR Memory Map1156
-
OTG_FS Registers1160
-
(Otg_Dieptxf0)1180
-
(Otg_Hnptxsts)1181
-
(Otg_Hptxfsiz)1188
-
FIFO Number)1188
-
(Otg_Hfnum)1191
-
(Otg_Hptxsts)1191
-
(Otg_Haintmsk)1193
-
(X = 01196
-
(X = 01197
-
(X = 01198
-
(X = 01199
-
(Otg_Diepmsk)1205
-
(Otg_Doepmsk)1206
-
(Otg_Daintmsk)1208
-
OTG Device1208
-
(Otg_Dvbusdis)1208
-
OTG Device1209
-
(Otg_Dvbuspulse)1209
-
(Otg_Diepempmsk)1209
-
(Otg_Diepctl0)1210
-
(X = 11211
-
(X = 01214
-
(Otg_Dieptsiz0)1215
-
Endpoint Number)1216
-
(X = 11217
-
(Otg_Doepctl0)1218
-
(X = 01219
-
(Otg_Doeptsiz0)1221
-
(X = 11222
-
Core Initialization1234
-
Host Initialization1234
-
Debug Support (DBG)1284
-
Overview1284
-
SWJ Debug Port Pins1287
-
JTAG TAP Connection1289
-
MCU Device ID Code1291
-
Boundary Scan TAP1291
-
JTAG Debug Port1292
-
SW Debug Port1294
-
SW Protocol Sequence1294
-
SW-DP Registers1296
-
SW-AP Registers1297
-
Core Debug1298
-
General Description1300
-
General Description1302
-
Main ETM Registers1302
-
Introduction1307
-
TRACE Pin Assignment1309
-
TPUI Formatter1310
-
Synchronous Mode1311
-
Asynchronous Mode1312
-
TPIU Registers1312
-
DBG Register Map1314
-
Flash Size1316
-
Revision History1318
Advertisement
Advertisement