ST STM32F40 Series Reference Manual page 1056

RM0090
Bit 8 SRPCAP: SRP-capable
The application uses this bit to control the OTG_FS controller's SRP capabilities. If the core
operates as a non-SRP-capable
B-device, it cannot request the connected A-device (host) to activate V
session.
0: SRP capability is not enabled.
1: SRP capability is enabled.
Note: Accessible in both device and host modes.
Bit 7 Reserved, must be kept at reset value.
Bit 6 PHYSEL: Full Speed serial transceiver select
This bit is always 1 with write-only access.
Bits5:3 Reserved, must be kept at reset value.
Bits 2:0 TOCAL: FS timeout calibration
The number of PHY clocks that the application programs in this field is added to the full-
speed interpacket timeout duration in the core to account for any additional delays introduced
by the PHY. This can be required, because the delay introduced by the PHY in generating the
line state condition can vary from one PHY to another.
The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The
application must program this field based on the speed of enumeration. The number of bit
times added per PHY clock is 0.25 bit times.
Doc ID 018909 Rev 4
USB on-the-go full-speed (OTG_FS)
BUS
and start a
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