Otg_Fs Global Registers; Table 174. Data Fifo (Dfifo) Access Register Map; Table 175. Power And Clock Gating Control And Status Registers - ST STM32F40 Series Reference Manual

RM0090

Table 174. Data FIFO (DFIFO) access register map

Device IN Endpoint 0/Host OUT Channel 0: DFIFO Write Access
Device OUT Endpoint 0/Host IN Channel 0: DFIFO Read Access
Device IN Endpoint 1/Host OUT Channel 1: DFIFO Write Access
Device OUT Endpoint 1/Host IN Channel 1: DFIFO Read Access
...
Device IN Endpoint x
Device OUT Endpoint x
1. Where x is 3 in device mode and 7 in host mode.
Power and clock gating CSR map
There is a single register for power and clock gating. It is available in both host and device
modes.

Table 175. Power and clock gating control and status registers

Power and clock gating control register
Reserved
30.16.2

OTG_FS global registers

These registers are available in both host and device modes, and do not need to be
reprogrammed when switching between these modes.
Bit values in the register descriptions are expressed in binary unless otherwise specified.
OTG_FS control and status register (OTG_FS_GOTGCTL)
Address offset: 0x000
Reset value: 0x0000 0800
The OTG_FS_GOTGCTL register controls the behavior and reflects the status of the OTG
function of the core.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
FIFO access register section
(1)
/Host OUT Channel x
(1)
/Host IN Channel x
Register name
r r r
Doc ID 018909 Rev 4
USB on-the-go full-speed (OTG_FS)
(1)
: DFIFO Write Access
(1)
: DFIFO Read Access
Acronym
PCGCR
Reserved
r rw rw rw
Address range
0x1000–0x1FFC
0x2000–0x2FFC
...
0xX000h–0xXFFCh
Offset address: 0xE00–0xFFF
0xE00-0xE04
0xE05–0xFFF
9 8 7 6 5 4 3
Reserved
r
Access
w
r
w
r
...
w
r
2 1 0
rw r
1050/1422