Rcc Dedicated Clocks Configuration Register (Rcc_Dckcfgr) - ST STM32F410 Reference Manual

RM0401
5.3.17

RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR)

Address offset: 0x8C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:27 Reserved, must be kept at reset value.
Bits 26:25 I2SSRC: I2S APB clock source selection
Bit 24 TIMPRE: Timers clocks prescalers selection
Bits 23: 0 Reserved, must be kept at reset value.
27 26 25
Res. I2SSCR
rw rw
11 10 9
Res. Res. Res.
Set and reset by software to configure the frequency of the I2S clock. These bits must be
written when the PLL is disabled.
00: I2S clock frequency = f
01: I2S clock frequency = Alternate function input frequency
1x: I2S clock frequency = HSI/HSE depending on PLLRC (bit 22 of RCC_PLLCFGR
register)
Set and reset by software to control the clock frequency of all the timers connected to APB1
and APB2 domain.
0: If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register) is configured to a
division factor of 1, TIMxCLK = HCKL. Otherwise, the timer clock frequencies are set to
twice to the frequency of the APB domain to which the timers are connected:
TIMxCLK = 2xPCLKx.
1:If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register) is configured to a
division factor of 1 or 2, TIMxCLK = HCKL. Otherwise, the timer clock frequencies are set to
four times to the frequency of the APB domain to which the timers are connected:
TIMxCLK = 4xPCLKx.
24 23 22
TIMPRE Res. Res. Res.
rw
8 7 6
Res. Res. Res. Res.
PPLCLK_R
RM0401 Rev 3
Reset and clock control (RCC)
21 20 19 18
Res. Res. Res.
5 4 3 2
Res. Res. Res.
17 16
Res. Res.
1 0
Res. Res.
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