Figure 7.3 Program/Program-Verify Flowchart - Renesas H8 Series Hardware Manual

Section 7 ROM
8. The maximum number of repetitions of the program/program-verify sequence of the same bit
is 1,000.
Write pulse application subroutine
Apply Write Pulse
WDT enable
Set PSU bit in FLMCR1
Wait 50 µs
Set P bit in FLMCR1
Wait (Wait time=programming time)
Clear P bit in FLMCR1
Wait 5 µs
Clear PSU bit in FLMCR1
Wait 5 µs
Disable WDT
End Sub
Notes: *The RTS instruction must not be used during the following 1. and 2. periods.
1. A period between 128-byte data programming to flash memory and the P bit clearing
2. A period between dummy writing of H'FF to a verify address and verify data reading
Rev. 1.00 Aug. 28, 2006 Page 108 of 400
REJ09B0268-0100
Store 128-byte program data in program
*
data area consecutively to flash memory
Increment address
Additional-programming data computation
No
Successively write 128-byte data from additional-
programming data area in RAM to flash memory

Figure 7.3 Program/Program-Verify Flowchart

START
Set SWE bit in FLMCR1
Wait 1 µs
data area and reprogram data area
n= 1
m= 0
Write 128-byte data in RAM reprogram
Apply
Write pulse
Set PV bit in FLMCR1
Wait 4 µs
Set block start address as
verify address
H'FF dummy write to verify address
Wait 2 µs
*
Read verify data
Verify data = No
write data?
Yes
No
≤
n 6 ?
Yes
Reprogram data computation
128-byte
data verification completed?
Yes
Clear PV bit in FLMCR1
Wait 2 µs
No
≤
n 6?
Yes
Sub-Routine-Call
Apply Write Pulse
No
m= 0 ?
Yes
Clear SWE bit in FLMCR1
Wait 100 µs
End of programming
n ← n + 1
m = 1
Yes
n ≤ 1000 ?
No
Clear SWE bit in FLMCR1
Wait 100 µs
Programming failure