Figure 7.3 Program/Program-Verify Flowchart - Renesas H8 Series Hardware Manual

Section 7 ROM
Write pulse application subroutine
Apply Write Pulse
WDT enable
Set PSU bit in FLMCR1
Wait 50 µs
Set P bit in FLMCR1
Wait (Wait time = Programming time)
Clear P bit in FLMCR1
Wait 5 µs
Clear PSU bit in FLMCR1
Wait 5 µs
Disable WDT
End Sub
Notes: 1. The RTS instruction must not be used during the following (1) and (2) periods.
(1) A period between 64-byte data programming to flash memory and the P bit clearing
(2) A period between dummy writing of H'FF to a verify address and verify data reading
2. When WDT is in use, disable it once.
Rev. 3.00 Sep. 14, 2006 Page 108 of 408
REJ09B0105-0300
Store 64-byte program data in program
*
1
Write 64-byte data in RAM reprogram
data area consecutively to flash memory
Increment address
Additional-programming data computation
No
Successively write 64-byte data from additional-
programming data area in RAM to flash memory

Figure 7.3 Program/Program-Verify Flowchart

START
*
Disable WDT
Set SWE bit in FLMCR1
Wait 1 µs
data area and reprogram data area
n = 1
m= 0
Apply
Write pulse
Set PV bit in FLMCR1
Wait 4 µs
Set block start address as
verify address
H'FF dummy write to verify address
Wait 2 µs
Read verify data
No
Verify data =
Write data?
Yes
No
≤
n 6 ?
Yes
Reprogram data computation
64-byte
data verification completed?
Yes
Clear PV bit in FLMCR1
Wait 2 µs
No
≤
n 6?
Yes
Sub-Routine-Call
Apply Write Pulse
No
m = 0 ?
Yes
Clear SWE bit in FLMCR1
Wait 100 µs
End of programming
2
n ← n + 1
*
1
m = 1
Yes
n ≤ 1000 ?
No
Clear SWE bit in FLMCR1
Wait 100 µs
Programming failure