Figure 6.10 Program/Program-Verify Flowchart - Renesas H8/3847R Series Hardware Manual

Section 6 ROM
Write pulse application subroutine
Apply Write Pulse
WDT enable
Set PSU bit in FLMCR1
Wait 50 µs
Set P bit in FLMCR1
Wait (Wait time = programming time)
Clear P bit in FLMCR1
Wait 5 µs
Clear PSU bit in FLMCR1
Wait 5 µs
Disable WDT
End Sub
Rev. 6.00 Aug 04, 2006 page 182 of 680
REJ09B0145-0600
Set SWE bit in FLMCR1
Store 128-byte program data in program
data area and reprogram data area
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Set block start address as
H'FF dummy write to verify address
Increment address
Additional-programming data
Reprogram data computation
No
Clear PV bit in FLMCR1
Successively write 128-byte data from
additional-programming data area
in RAM to flash memory
Clear SWE bit in FLMCR1

Figure 6.10 Program/Program-Verify Flowchart

START
Wait 1 µs
n = 1
m = 0
Apply Write pulse
Set PV bit in FLMCR1
Wait 4 µs
verify address
Wait 2 µs
Read verify data
No
Verify data =
write data?
m = 1
Yes
No
n ≤ 6 ?
Yes
computation
128-byte
data verification
completed?
Yes
Wait 2 µs
No
n ≤ 6?
Yes
Sub-Routine-Call
Apply Write Pulse
No
m = 0 ?
Yes
Wait 100 µs
End of programming
n ← n + 1
Yes
n ≤ 1000 ?
No
Clear SWE bit in FLMCR1
Wait 100 µs
Programming failure