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4.4 Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is
set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1
in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a
start address from a vector table entry corresponding to a vector number from 0 to 3, which is
specified in the instruction code.
4.5 Stack Status after Exception Handling
Figure 4-4 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
SP-4
SP-3
SP-2
SP-1
SP (ER7) →
Before exception handling
Legend
PCE:
Bits 23 to 16 of program counter (PC)
PCH:
Bits 15 to 8 of program counter (PC)
PCL:
Bits 7 to 0 of program counter (PC)
CCR:
Condition code register
SP:
Stack pointer
Notes:
1.
PC indicates the address of the first instruction that will be executed after return.
2.
Saving and restoring of registers must be conducted at even addresses in word-size
or longword-size units.
Figure 4-4 Stack after Completion of Exception Handling (Advanced Mode)
Stack area
Save on stack
→
SP (ER7)
SP+1
SP+2
SP+3
SP+4
After exception handling
CCR
PC
E
PC
H
PC
L
Even address
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