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4.5 Stack Status after Exception Handling
Figure 4-5 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
SP-4
SP-3
SP-2
SP-1
SP (ER7) →
SP-4
SP-3
SP-2
SP-1
SP (ER7) →
Legend
PCE:
PCH:
PCL:
CCR:
SP:
Notes:
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Stack area
Before exception handling
Stack area
Before exception handling
Bits 23 to 16 of program counter (PC)
Bits 15 to 8 of program counter (PC)
Bits 7 to 0 of program counter (PC)
Condition code register
Stack pointer
*
Ignored upon return.
1.
This is the address of the first instruction executed after return.
2.
Saving and restoring of registers must be conducted at even addresses in word-size
or longword-size units.
Figure 4-5 Stack after Completion of Exception Handling
→
SP (ER7)
CCR
SP+1
CCR
PC
SP+2
SP+3
PC
SP+4
After exception handling
Save on stack
a. Normal mode
→
SP (ER7)
CCR
SP+1
PC
SP+2
PC
SP+3
PC
SP+4
After exception handling
Save on stack
b. Advanced mode
72
*
H
L
Even address
E
H
L
Even address
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