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4.5
Stack Status after Exception Handling
Figure 4.6 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
SP–4
SP–3
SP–2
SP–1
SP (ER7) →
Before exception handling
SP–4
SP–3
SP–2
SP–1
SP (ER7) →
Before exception handling
Legend
PC
:
Bits 23 to 16 of program counter (PC)
E
PC
:
Bits 15 to 8 of program counter (PC)
H
PC
:
Bits 7 to 0 of program counter (PC)
L
CCR:
Condition code register
SP:
Stack pointer
Notes:
*
Ignored at return.
1.
PC indicates the address of the first instruction that will be executed after return.
2.
Registers must be saved in word or longword size at even addresses.
Figure 4.6 Stack after Completion of Exception Handling
Stack area
Pushed on stack
a. Normal mode
Stack area
Pushed on stack
b. Advanced mode
→
SP (ER7)
SP+1
SP+2
SP+3
SP+4
After exception handling
→
SP (ER7)
SP+1
SP+2
SP+3
SP+4
After exception handling
CCR
CCR
*
PC
H
PC
L
Even address
CCR
PC
E
PC
H
PC
L
Even address
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