System Control Register: Power-Down Control Bits - Hitachi H8/329 Series Hardware Manual

12.2 System Control Register: Power-Down Control Bits

Bits 7 to 4 of the system control register (SYSCR) concern the power-down state. Specifically,
they concern the software standby mode.
Table 12-2 lists the attributes of the system control register.
Table 12-2. System Control Register
Name
System control register
Bit 7
SSBY
Initial value 0
Read/Write R/W
Bit 7—Software Standby (SSBY): This bit enables or disables the transition to the software
standby mode.
On recovery from the software standby mode by an external interrupt, SSBY remains set to "1."
To clear this bit, software must write a "0."
Bit 7
SSBY Description
0 The SLEEP instruction causes a transition to the sleep mode.
1 The SLEEP instruction causes a transition to the software
standby mode.
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling
time when the chip recovers from the software standby mode by an external interrupt. During the
selected time, the clock oscillator runs but clock pulses are not supplied to the CPU or the on-chip
supporting modules.
Abbreviation R/W
SYSCR R/W
6 5 4
STS2 STS1 STS0
0 0 0
R/W R/W R/W
240
Initial value Address
H'0B H'FFC4
3 2 1
— NMIEG —
1 0 1
— R/W —
0
RAME
1
R/W
(Initial value)