Bit Rate Register (Brr) - Hitachi H8/3664 Hardware Manual

Bit 1—Multiprocessor Bit Receive (MPBR): Bit 1 stores the multiprocessor bit in a receive
character during multiprocessor format reception in asynchronous mode.
Bit 1 is a read-only bit and cannot be modified.
Bit 1: MPBR
0
1
Note: * When bit RE is cleared to 0 in SCR3 with the multiprocessor format, bit MPBR is not
affected and retains its previous state.
Bit 0—Multiprocessor Bit Transfer (MPBT): Bit 0 stores the multiprocessor bit added to
transmit data when transmitting in asynchronous mode. The bit MPBT setting is invalid when
synchronous mode is selected, when the multiprocessor communication function is disabled, and
when not transmitting.
Bit 0: MPBT
0
1
14.2.8

Bit Rate Register (BRR)

Bit 7
BRR7
Initial value 1
Read/Write R/W
BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud
rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR).
BRR can be read or written by the CPU at any time.
BRR is initialized to H'FF upon reset, and in standby, subactive, or subsleep mode.
Table 14.3 shows examples of BRR settings in asynchronous mode. The values shown are for
active (high-speed) mode.
260
Description
Data in which the multiprocessor bit is 0 has been received
Data in which the multiprocessor bit is 1 has been received
Description
Multiprocessor bit value in transmit data is 0
Multiprocessor bit value in transmit data is 1
6
BRR6 BRR5
1
R/W R/W
5 4
BRR4 BRR3
1 1
R/W R/W
*
3 2
BRR2 BRR1
1 1
R/W R/W
(Initial value)
(Initial value)
1 0
BRR0
1 1
R/W