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10.2.2 Timer Control/Status Register (TCSR)
TCSR is an 8-bit readable and writable*
and clock source.
Bit
OVF
Initial value
Read/Write
R/(W)
Overflow flag
Status flag indicating overflow
Bits 7 to 5 are initialized to 0 by a reset and in standby mode. Bits 2 to 0 are initialized to 0 by a
reset. In software standby mode bits 2 to 0 are not initialized, but retain their previous values.
Notes: 1. TCSR is write-protected by a password. For details see section 10.2.4, Notes on
Register Access.
2. Only 0 can be written to clear the flag.
1
7
6
WT/IT
TME
0
0
*2
R/W
R/W
Timer enable
Selects whether TCNT runs or halts
Timer mode select
Selects the mode
register. Its functions include selecting the timer mode
5
4
—
—
0
1
—
—
Reserved bits
3
2
CKS2
CKS1
1
0
R/W
R/W
Clock select
These bits select the
TCNT clock source
1
0
CKS0
0
0
R/W
311
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