Pin Configuration; Register Configuration; Timer Counter (Tcnt); Timer Control/Status Register (Tcsr) - Hitachi H8S/2338 Series Hardware Manual

10.1.3

Pin Configuration

Table 10-1 describes the WDT output pin.
Table 10-1 WDT Pin
Name
Watchdog timer overflow
Note: * The WDTOVF output function is not available in all models; please check the reference
manual for the relevant model for confirmation.
10.1.4

Register Configuration

The WDT has three registers, as summarized in table 10-2. These registers control clock selection,
WDT mode switching, and the reset signal.
Table 10-2 WDT Registers
Name
Timer control/status register
Timer counter
Reset control/status register
Notes: 1. Lower 16 bits of the address.
2. For details of write operations, see section 10.2.4, Notes on Register Access.
3. Only a write of 0 is permitted to bit 7, to clear the flag.
Symbol I/O
WDTOVF* Output
Abbreviation R/W
TCSR R/(W)*
TCNT R/W
RSTCSR R/(W)*
Function
Outputs counter overflow signal in watchdog
timer mode
Initial Value
3
H'18
H'00
3
H'1F
1
Address*
2
Write* Read
H'FFBC H'FFBC
H'FFBC H'FFBD
H'FFBE H'FFBF
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