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10.3.2
Timer Mode Register (TMDR)
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of
each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings
should be changed only when TCNT operation is stopped.
Bit
Bit Name
Initial value
7, 6
All 1
5
BFB
0
4
BFA
0
3
MD3
0
2
MD2
0
1
MD1
0
0
MD0
0
R/W
Description
Reserved
These bits are always read as 1 and cannot be
modified.
R/W
Buffer Operation B
Specifies whether TGRB is to operate in the normal
way, or TGRB and TGRD are to be used together for
buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not
generated.
In channels 1, 2, 4, and 5, which have no TGRD, bit
5 is reserved. It is always read as 0 and cannot be
modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer
operation
R/W
Buffer Operation A
Specifies whether TGRA is to operate in the normal
way, or TGRA and TGRC are to be used together for
buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not
generated.
In channels 1, 2, 4, and 5, which have no TGRC, bit
4 is reserved. It is always read as 0 and cannot be
modified.
0: TGRA operates normally
1:TGRA and TGRC used together for buffer
operation
R/W
Modes 0 to 3
R/W
These bits are used to set the timer operating mode.
R/W
MD3 is a reserved bit. In a write, it should always be
R/W
written with 0. See table 10.11 for details.
Rev. 1.0, 09/02, page 171 of 568
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