Timer Mode Register (Tmdr) - Hitachi H8/3006 Hardware Manual

Bit 0—Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or
synchronously.
Bit 0
SYNC0 Description
0 Channel 0's timer counter (16TCNT0) operates independently
16TCNT0 is preset and cleared independently of other channels
1 Channel 0 operates synchronously
16TCNT0 can be synchronously preset and cleared
9.2.3

Timer Mode Register (TMDR)

TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 2. It also
selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.
Bit
—
Initial value
Read/Write —
Reserved bit
TMDR is initialized to H'98 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in
phase counting mode.
Bit 6
MDF Description
0 Channel 2 operates normally
1 Channel 2 operates in phase counting mode
290
7 6 5
MDF FDIR
1 0 0
R/W R/W
Flag direction
Selects the setting condition for the overflow
flag (OVF) in TISRC
Phase counting mode flag
Selects phase counting mode for channel 2
4 3 2
— — PWM2
1 1 0
— — R/W
PWM mode 2 to 0
These bits select PWM
Reserved bit
mode for channels 2 to 0
(Initial value)
1 0
PWM1 PWM0
0 0
R/W R/W
(Initial value)