Timer Mode Register (Tmdr) - Hitachi H8/3032 Series Hardware Manual

8.2.3 Timer Mode Register (TMDR)

TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 4. It also
selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.
Bit
Initial value
Read/Write
TMDR is initialized to H'80 by a reset and in standby mode.
Bit 7—Reserved: Read-only bit, always read as 1.
Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in
phase counting mode.
Bit 6
MDF
0
1
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7 6
— MDF FDIR
1 0
— R/W R/W
Flag direction
Selects the setting condition for the overflow
flag (OVF) in timer status register 2 (TSR2)
Phase counting mode flag
Selects phase counting mode for channel 2
Reserved bit
Description
Channel 2 operates normally
Channel 2 operates in phase counting mode
5 4 3 2
PWM4 PWM3 PWM2
0 0 0 0
R/W R/W R/W
PWM mode 4 to 0
These bits select PWM
mode for channels 4 to 0
184
1 0
PWM1 PWM0
0 0
R/W R/W
(Initial value)