Timer Mode Register (Tmdr) - Hitachi H8/3062 Hardware Manual

Bit 1—Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or
synchronously.
Bit 1
SYNC1 Description
0 Channel 1's timer counter (16TCNT1) operates independently
16TCNT1 is preset and cleared independently of other channels
1 Channel 1 operates synchronously
16TCNT1 can be synchronously preset and cleared
Bit 0—Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or
synchronously.
Bit 0
SYNC0 Description
0 Channel 0's timer counter (16TCNT0) operates independently
16TCNT0 is preset and cleared independently of other channels
1 Channel 0 operates synchronously
16TCNT0 can be synchronously preset and cleared
8.2.3

Timer Mode Register (TMDR)

TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 2. It also
selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.
Bit
Initial value
Read/Write
Reserved bit
TMDR is initialized to H'98 by a reset and in standby mode.
226
7 6
— MDF FDIR
1 0
— R/W R/W
Flag direction
Selects the setting condition for the overflow
flag (OVF) in TISRC
Phase counting mode flag
Selects phase counting mode for channel 2
5 4
— —
0 1
— —
Reserved bit
3 2
PWM2 PWM1
1 0
R/W R/W
PWM mode 2 to 0
These bits select PWM
mode for channels 2 to 0
(Initial value)
(Initial value)
1 0
PWM0
0 0
R/W