Timer Mode Register (Tmdr) - Hitachi H8S/2215 Series Hardware Manual

10.3.2

Timer Mode Register (TMDR)

The TMDR registers are used to set the operating mode for each channel. The TPU has three
TMDR registers, one for each channel. TMDR register settings should be made only when TCNT
operation is stopped.
Bit Bit Name Initial value
7 – 1
6 – 1
5 BFB 0
4 BFA 0
3 MD3 0
2 MD2 0
1 MD1 0
0 MD0 0
R/W Description
– Reserved:
– These bits are always read as 1 and cannot be modified.
R/W Buffer Operation B
Specifies whether TGRB is to operate in the normal way,
or TGRB and TGRD are to be used together for buffer
operation. When TGRD is used as a buffer register.
TGRD input capture/output compare is not generation. In
channels 1 and 2, which have no TGRD, bit 5 is reserved.
It is always read as 0 and cannot be modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer operation
R/W Buffer Operation A
Specifies whether TGRA is to operate in the normal way,
or TGRA and TGRC are to be used together for buffer
operation. When TGRC is used as a buffer register,
TGRC input capture/output compare is not generated. In
channels 1 and 2, which have no TGRC, bit 4 is reserved.
It is always read as 0 and cannot be modified.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer operation
R/W Modes 3 to 0
R/W These bits are used to set the timer operating mode.
R/W MD3 is a reserved bit. In a write, the write value should
always be 0. See table 10.8, for details.
R/W
Rev. 3.0, 10/02, page 273 of 686