Sleep Mode; Transition To The Sleep Mode; Canceling The Sleep Mode; Standby Mode - Hitachi SH7095 Hardware User Manual

Bit 0: MSTP0 Description
0 SCI running (Initial value).
1 Clock supply to SCI halted.
14.3

Sleep Mode

14.3.1

Transition to the Sleep Mode

Executing the SLEEP instruction when the SBY bit of SBYCR is 0 causes a transition from the
program execution state to the sleep mode. Although the CPU halts immediately after executing
the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip
peripheral modules continue to run during the sleep mode.
14.3.2

Canceling the Sleep Mode

The sleep mode is canceled by an interrupt, DMA address error, power-on reset, or manual reset.
Cancellation by an Interrupt: When an interrupt occurs, the sleep mode is canceled and interrupt
exception processing is executed. The sleep mode is not canceled if the interrupt cannot be
accepted because its priority level is equal to or less than the mask level set in the CPU's status
register (SR) or if an interrupt by an on-chip peripheral module is disabled at the peripheral
module.
Cancellation by a DMA Address Error: If a DMA address error occurs, the sleep mode is
canceled and DMA address error exception processing is executed.
Cancellation by a Power-On Reset: A power-on reset cancels the sleep mode.
Cancellation by a Manual Reset: A manual reset cancels the sleep mode.
14.4

Standby Mode

14.4.1

Transition to the Standby Mode

To enter the standby mode, set the SBY bit to 1 in SBYCR, then execute the SLEEP instruction.
The LSI moves from the program execution state to the standby mode. The NMI interrupt cannot
be accepted during five cycles at the time and after the SLEEP instruction is executed. In the
standby mode, power consumption is greatly reduced by halting not only the CPU, but the clock
and on-chip peripheral modules as well. CPU register contents are held, and some on-chip
peripheral modules are initialized.
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