Sleep Mode; Transition To Sleep Mode - Hitachi H8/3827R Series Hardware Manual

Bits 1 and 0: Subactive mode clock select (SA1 and SA0)
These bits select the CPU clock rate (ø
cannot be modified in subactive mode.
Bit 1 Bit 0
SA1 SA0
0 0
0 1
1
*
5.2

Sleep Mode

5.2.1

Transition to Sleep Mode

1. Transition to sleep (high-speed) mode
The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is
executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON and DTON bits
in SYSCR2 are cleared to 0. In sleep mode CPU operation is halted but the on-chip peripheral
functions. CPU register contents are retained.
2. Transition to sleep (medium-speed) mode
The system goes from active mode to sleep (medium-speed) mode when a SLEEP instruction is
executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2
is set to 1, and the DTON bit in SYSCR2 is cleared to 0. In sleep (medium-speed) mode, as in
sleep (high-speed) mode, CPU operation is halted but the on-chip peripheral functions are
operational. The clock frequency in sleep (medium-speed) mode is determined by the MA1 and
MA0 bits in SYSCR1. CPU register contents are retained.
Furthermore, it sometimes acts with half state early timing at the time of transition to sleep
(medium-speed) mode.
102
/2, ø /4, or ø
W W
Description
ø /8
W
ø /4
W
ø /2
W
/8) in subactive mode. SA1 and SA0
W
(initial value)
* : Don't care