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8.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode
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When the chip is reset or enters hardware or software standby mode, the DMAC is initialized and
halts. DMAC operations continue in sleep mode. Figure 8-24 shows the timing of a cycle-steal
transfer in sleep mode.
CPU cycle
T
T
2
d
ø
Address bus
RD
HWR LWR
,
Figure 8-24 Timing of Cycle-Steal Transfer in Sleep Mode
DMAC cycle
T
T
T
T
1
2
1
2
236
Sleep mode
DMAC cycle
T
T
T
T
T
d
1
2
1
2
T
d
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