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22.3
Sleep Mode
22.3.1
Transition to Sleep Mode
When the SLEEP instruction is executed when the SSBY bit in SBYCR is 0, the CPU enters the
sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers
are retained. Other supporting modules do not stop.
22.3.2
Exiting Sleep Mode
Sleep mode is exited by any interrupt, or signals at the RES, MRES and STBY pins.
• Exiting Sleep Mode by Interrupts
When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep
mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the
CPU.
• Exiting Sleep Mode by RES or MRES Pin
Setting the RES or MRES pin level Low selects the reset state. After the stipulated reset input
duration, driving the RES or MRES pin High starts the CPU performing reset exception
processing.
• Exiting Sleep Mode by STBY Pin
When the STBY pin level is driven Low, a transition is made to hardware standby mode.
22.4
Software Standby Mode
22.4.1
Transition to Software Standby Mode
A transition is made to software standby mode when the SLEEP instruction is executed when the
SSBY bit in SBYCR is 1. In this mode, the CPU, on-chip supporting modules, and oscillator all
stop. However, the contents of the CPU's internal registers, RAM data, and the states of on-chip
supporting modules other than the A/D converter, and the states of I/O ports, are retained. In this
mode the oscillator stops, and therefore power dissipation is significantly reduced.
Rev. 3.0, 10/02, page 615 of 686
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