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6.2.1
Sleep Mode
In the sleep mode, CPU operation is halted but the on-chip peripheral modules function at the
clock frequency set by the MA2 to MA0 bits in SYSCR2. CPU register contents are retained.
When an interrupt is requested, the sleep mode is cleared and interrupt exception handling starts.
The sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the
requested interrupt is disabled in the interrupt enable register. a transition is made to subactive
mode when the bit is 1.
When the RES pin goes low, the CPU goes into the reset state and the sleep mode is cleared.
6.2.2
Standby Mode
In the standby mode, the clock pulse generator stops, so the CPU and on-chip peripheral modules
stop functioning. However, as long as the rated voltage is supplied, the contents of CPU registers,
on-chip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents
will be retained as long as the voltage set by the RAM data retention voltage is provided. The I/O
ports go to the high-impedance state.
The standby mode is cleared by an interrupt. When an interrupt is requested, the system clock
pulse generator starts. After the time set in bits STS2–STS0 in SYSCR1 has elapsed, and interrupt
exception handling starts. The standby mode is not cleared if the I bit of CCR is set to 1 or the
requested interrupt is disabled in the interrupt enable register.
When the RES pin goes low, the system clock pulse generator starts. Since system clock signals
are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the
RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
6.2.3
Subsleep Mode
In the subsleep mode, the system clock oscillator is halted, and operation of the CPU and on-chip
peripheral modules is halted. As long as a required voltage is applied, the contents of CPU
registers, the on-chip RAM, and some registers of the on-chip peripheral modules are retained. I/O
ports keep the same states as before the transition.
The subsleep mode is cleared by an interrupt. When an interrupt is requested, the system clock
oscillator starts to oscillate.
The subsleep mode is cleared and an interrupt exception handling starts when the time set in bits
STS2 to STS0 in SYSCR1 elapses.
The subsleep mode is not cleared if the I bit of CCR is 1 or the interrupt is disabled in the interrupt
enable bit.
Rev. 1.0, 03/01, page 71 of 280
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