Sleep Mode; Transition To Sleep Mode - Hitachi H8/3035 Series Hardware Manual

Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software
standby mode is exited by an external interrupt, this bit remains set to 1 after the return to
normal operation. To clear this bit, write 0.
Bit 7
SSBY Description
0 SLEEP instruction causes transition to sleep mode
1 SLEEP instruction causes transition to software standby mode
Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the
CPU and on-chip supporting modules wait for the clock to settle when software standby mode is
exited by an external interrupt. If the clock is generated by a crystal resonator, set these bits
according to the clock frequency so that the waiting time (for the clock to stabilize) will be at
least 8 ms. See table 16-3. If an external clock is used, any setting is permitted.
Bit 6 Bit 5
STS2 STS1
0 0
1
1 0
1

16.3 Sleep Mode

16.3.1 Transition to Sleep Mode

When the SSBY bit is cleared to 0 in the system control register (SYSCR), execution of the
SLEEP instruction causes a transition from the program execution state to sleep mode.
Immediately after executing the SLEEP instruction the CPU halts, but the contents of its internal
registers are retained. The on-chip supporting modules do not halt in sleep mode.
Bit 4
STS0 Description
0 Waiting time = 8192 states
1 Waiting time = 16384 states
0 Waiting time = 32768 states
1 Waiting time = 65536 states
— Waiting time = 131072 states
— Illegal setting
(Initial value)
(Initial value)
385