Break Bus Cycle Register A (Bbra) - Hitachi SH7095 Hardware User Manual

• BAMRAL Bits 15 to 0—Break Address Mask A 15 to 0 (BAMA15 to BAMA0): These bits
specify whether bits 15–0 (BAA15 to BAA0) of the channel A break address set in BARAL
are masked or not.
Bits 31– 0: BAMAn
0
1
n = 31 to 0
6.2.3

Break Bus Cycle Register A (BBRA)

Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
The break bus cycle register A (BBRA) is a 16-bit read/write register that selects the following
four channel A break conditions:
1. CPU cycle/peripheral cycle.
2. Instruction fetch/data access.
3. Read/write.
4. Operand size.
A power-on reset initializes BBRA to H'0000.
• Bits 15 to 8—Reserved bits: These bits always read 0. The write value should always be 0.
100 Hitachi
Description
Channel A break address BAAn is included in the break conditions
(initial value).
Channel A break address BAAn is masked and therefore not included
in the break conditions
15 14
— —
0 0
R R
7 6
CPA1 CPA0
0 0
R/W R/W
13 12
— —
0 0
R R
5 4
IDA1 IDA0 RWA1
0 0
R/W R/W
11 10
— —
0 0
R R
3 2
RWA0 SZA1
0 0
R/W R/W
9 8
— —
0 0
R R
1 0
SZA0
0 0
R/W R/W