Irq Status Register (Isr) - Hitachi H8/3035 Series Hardware Manual

5.2.3 IRQ Status Register (ISR)

ISR is an 8-bit readable/writable register that indicates the status of IRQ
requests.
Bit 7
—
Initial value 0
Read/Write —
Note: * Only 0 can be written, to clear flags.
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 5—Reserved: These bits cannot be modified and are always read as 0.
Bits 4 to 0—IRQ to IRQ
4
IRQ interrupt requests.
0
Bits 4 to 0
IRQ4F to IRQ0F Description
0 [Clearing conditions]
0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.
IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried out.
IRQnSC = 1 and IRQn interrupt exception handling is carried out.
1 [Setting conditions]
IRQnSC = 0 and IRQn input is low.
IRQnSC = 1 and IRQn input changes from high to low.
Note: n = 4 to 0
6 5
— — IRQ4F
0 0
— — R/(W) *
Reserved bits
Flags (IRQ4F to IRQ0F): These bits indicate the status of IRQ
0
to IRQ
0
4 3 2
IRQ3F IRQ2F
0 0 0
R/(W) * R/(W) *
IRQ to IRQ flags
4 0
These bits indicate IRQ
interrupt request status
interrupt
4
1 0
IRQ1F IRQ0F
0 0
R/(W) *
R/(W) *
to IRQ
4 0
to
4
(Initial value)
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