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5.2.3 IRQ Status Register (ISR)
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ISR is an 8-bit readable/writable register that indicates the status of IRQ
requests.
Bit
7
—
Initial value
0
Read/Write
—
Reserved bits
Note:
Only 0 can be written, to clear flags.
*
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 0.
Bits 5 to 0—IRQ
to IRQ
5
IRQ
to IRQ
interrupt requests.
5
0
Bits 5 to 0
IRQ5F to IRQ0F
Description
0
[Clearing conditions]
0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.
IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried out.
IRQnSC = 1 and IRQn interrupt exception handling is carried out.
1
[Setting conditions]
IRQnSC = 0 and IRQn input is low.
IRQnSC = 1 and IRQn input changes from high to low.
Note: n = 5 to 0
6
5
—
IRQ5F
IRQ4F
0
0
—
R/(W) *
R/(W) *
Flags (IRQ
F to IRQ
0
5
0
92
to IRQ
0
4
3
2
IRQ3F
IRQ2F
0
0
0
R/(W) *
R/(W) *
IRQ to IRQ flags
5
0
These bits indicate IRQ to IRQ
interrupt request status
F): These bits indicate the status of
interrupt
5
1
0
IRQ1F
IRQ0F
0
0
R/(W) *
R/(W) *
5
0
(Initial value)
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