Functional Description - Freescale Semiconductor MCF5329 Reference Manual

Power Management
Field
7–6 Low-power mode select. Used to select the low-power mode the chip enters after the ColdFire core executes the
LPMD STOP instruction. These bits must be written prior to instruction execution for them to take effect. The LPMD bits are
readable and writable in all modes.
00 Run
01 Doze
10 Wait
11 Stop
Note: If LPCR[LPMD] is cleared, the device stops executing code upon issue of a STOP instruction. However, no
clocks are disabled.
5 Fast wake-up. Determines whether the system clocks are enabled upon wake-up from stop mode. This bit must be
FWKUP written before execution of the STOP instruction for it to take effect.
0 System clocks enabled only when PLL is locked or operating normally.
1 System clocks enabled upon wake-up from stop mode, regardless of PLL lock status.
Note: Setting this bit is potentially dangerous and unreliable. The system may behave unpredictably when using an
unlocked clock because the clock frequency could overshoot the maximum frequency of the device.
Note: If FWKUP is set before entering stop mode, it should not be cleared upon wake-up from stop mode until after
the PLL has actually acquired lock. Lock status may be obtained by reading the MISCCR[PLLLOCK] bit.
FWKUP is not effective in limp mode because the PLL never locks in this mode. The system clocks are always
enabled upon wake-up from stop mode, regardless of the value of FWKUP.
4–3 FB_CLK stop mode bits. Controls the operation of the clocks, PLL, and oscillator in stop mode as shown below.
STPMD
STPMD
2–0 Reserved, should be cleared.
8.3

Functional Description

The functions and characteristics of the low-power modes, and how each module is affected by, or affects
these modes are discussed in this section.
8.3.1 Peripheral Shut Down
All peripherals, except for the SCM and crossbar switch, may have their input clocks individually removed
by software to reduce power consumption. See
(PPMHR0, PPMHR1, & PPMLR0)"
remains disabled during any low-power mode of operation.
8.3.2 Limp mode
The device may also be booted into a low-frequency limp mode, in which the PLL is bypassed and the
device runs from a factor of the input clock (EXTAL). In this mode, EXTAL feeds a 5-bit programmable
8-8
Table 8-9. LPCR Field Descriptions
System Clocks FB_CLK
00 Disabled
01 Disabled Disabled
10 Disabled Disabled
11 Disabled Disabled
Section 8.2.4, "Peripheral Power Management Registers
for more information. A peripheral may be disabled at any time and
MCF5329 Reference Manual, Rev 3
Description
PLL
Enabled Enabled
Enabled
Disabled
Disabled
Oscillator
Enabled
Enabled
Enabled
Disabled
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