Memory Map/Register Definition - Freescale Semiconductor MCF5329 Reference Manual

29.2

Memory Map/Register Definition

The timer module registers, shown in
Address
DMA Timer 0
DMA Timer 1
DMA Timer 2
DMA Timer 3
0xFC07_0000 DMA Timer n Mode Register (DTMRn)
0xFC07_4000
0xFC07_8000
0xFC07_C000
0xFC07_0002 DMA Timer n Extended Mode Register (DTXMRn)
0xFC07_4002
0xFC07_8002
0xFC07_C002
0xFC07_0003 DMA Timer n Event Register (DTERn)
0xFC07_4003
0xFC07_8003
0xFC07_C003
0xFC07_0004 DMA Timer n Reference Register (DTRRn)
0xFC07_4004
0xFC07_8004
0xFC07_C004
0xFC07_0008 DMA Timer n Capture Register (DTCRn)
0xFC07_4008
0xFC07_8008
0xFC07_C008
0xFC07_000C DMA Timer n Counter Register (DTCNn)
0xFC07_400C
0xFC07_800C
0xFC07_C00C
29.2.1 DMA Timer Mode Registers (DTMRn)
DTMRs, shown in Figure
Address: 0xFC07_0000 (DTMR0)
0xFC07_4000 (DTMR1)
0xFC07_8000 (DTMR2)
0xFC07_C000 (DTMR3)
15 14 13
R
W
Reset 0 0 0
Freescale Semiconductor
Table 29-1, can be modified at any time.
Table 29-1. DMA Timer Module Memory Map
Register
29-2, program the prescaler and various timer modes.
12 11 10 9
PS
0 0 0 0
Figure 29-2. DTMRn Registers
MCF5329 Reference Manual, Rev 3
Width
Access
(bits)
16 R/W
8 R/W
8 R/W
32 R/W
32 R/W
32 R
8 7 6 5
CE OM ORRI FRR
0 0 0 0
DMA Timers (DTIM0–DTIM3)
Reset Value Section/Page
0x0000 29.2.1/29-3
0x00 29.2.2/29-4
0x00 29.2.3/29-5
0xFFFF_FFFF 29.2.4/29-6
0x0000_0000 29.2.5/29-7
0x0000_0000 29.2.6/29-8
Access: User read/write
4 3 2 1
CLK RST
0 0 0 0
29-3
0
0