Freescale Semiconductor MCF5329 Reference Manual page 353

If wait states are used, the S1 state repeats continuously until the the chip-select auto-acknowledge unit
asserts internal transfer acknowledge or the external FB_TA is recognized as asserted.
Figure 17-20 show a read and write cycle with one wait state.
FB_CLK
FB_A[23:0]
FB_D[31:X]
FB_R/W
FB_TS
FB_CSn, FB_OE,
FB_BE/BWEn
FB_TA
FB_A[23:0]
FB_D[31:X]
FB_CSn, FB_BE/BWEn
17.4.5.4.2 Address Setup and Hold
The timing of the assertion and negation of the chip selects, byte selects, and output enable can be
programmed on a chip-select basis. Each chip-select can be programmed to assert one to four clocks after
Freescale Semiconductor
S0 S1
ADDR[23:0]
ADDR[31:X]
Figure 17-19. Read-Bus Cycle (One Wait State)
S0 S1
FB_CLK
ADDR[31:X]
FB_R/W
FB_TS
FB_OE
FB_TA
Figure 17-20. Write-Bus Cycle (One Wait State)
MCF5329 Reference Manual, Rev 3
WS S2 S3
DATA
WS S2
ADDR[23:0]
DATA
FlexBus
Figure 17-19 and
S0
S3 S0
17-21