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UART Modules
31.4.5
Bus Operation
This section describes bus operation during read, write, and interrupt acknowledge cycles to the UART
module.
31.4.5.1
Read Cycles
The UART module responds to reads with byte data. Reserved registers return zeros.
31.4.5.2
Write Cycles
The UART module accepts write data as bytes only. Write cycles to read-only or reserved registers
complete normally without an error termination, but data is ignored.
31.5
Initialization/Application Information
The software flowchart,
•
UART module initialization—These routines consist of SINIT and CHCHK (See Sheet 1 p. 31-29
and Sheet 2 p. 31-30). Before SINIT is called at system initialization, the calling routine allocates
2 words on the system FIFO. On return to the calling routine, SINIT passes UART status data on
the FIFO. If SINIT finds no errors, the transmitter and receiver are enabled. SINIT calls CHCHK
to perform the checks. When called, SINIT places the UART in local loopback mode and checks
for the following errors:
— Transmitter never ready
— Receiver never ready
— Parity error
— Incorrect character received
•
I/O driver routine—This routine (See Sheet 4 p. 31-32 and Sheet 5 p. 31-33) consists of INCH, the
terminal input character routine which gets a character from the receiver, and OUTCH, which
sends a character to the transmitter.
•
Interrupt handling—This consists of SIRQ (See Sheet 4 p. 31-32), which is executed after the
UART module generates an interrupt caused by a change-in-break (beginning of a break). SIRQ
then clears the interrupt source, waits for the next change-in-break interrupt (end of break), clears
the interrupt source again, then returns from exception processing to the system monitor.
31.5.1
Interrupt and DMA Request Initialization
31.5.1.1
Setting up the UART to Generate Core Interrupts
The list below provides steps to properly initialize the UART to generate an interrupt request to the
processor's interrupt controller. See
assignments for the UART modules.
1. Initialize the appropriate ICRx register in the interrupt controller.
2. Unmask appropriate bits in IMR in the interrupt controller.
31-26
Figure
31-25, consists of:
Section 14.2.9.1, "Interrupt Sources,"
MCF5329 Reference Manual, Rev 3
for details on interrupt
Freescale Semiconductor
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