Security Assurance Features - Freescale Semiconductor MCF5329 Reference Manual

Symmetric Key Hardware Accelerator (SKHA)
35.3.4.4 SKHA Core
The heart of the SKHA is the core processing engine, Figure 35-22. The core contains the DES and AES
block cipher engines. Also, the cipher mode (ECB, CBC, CTR) is implemented in this block. The SKHA
logic block drives the cipher mode, algorithm, processing direction, key, and input block to the Mode
Control logic.
While DES and AES operate differently internally, the Mode Control logic operates on top of the AES and
DES engines. The Mode Control logic interfaces to both engines and feeds the input block and key to the
selected engine. When the selected engine processes a block, it returns a "done" signal with the output
block. The Mode Control logic in turn returns a "done" signal to the SKHA logic block along with the
processed message block.
When the entire message is processed (following write to the End of Message register), the SKHA logic
block sets SKSR[DONE] and generates an interrupt request to the interrupt controller. This indicates to
that it is safe to read context.
Output
Input
Mode Control
Logic
DES
AES
Engine
Engine
64 or 192
128
Key Data
Figure 35-22. SKHA Core Block Diagram
35.3.5

Security Assurance Features

The SKHA features simple security assurance features to prevent operation in the presence of hardware
faults and to shield visibility to sensitive data. Further, any user error or internal hardware fault causes the
internal state machines to enter an idle/error state. In this case, the SKHA must be reset to resume
operation, SKCMR[SWR]. Readable registers may be accessed to determine the nature of the error.
MCF5329 Reference Manual, Rev 3
35-18 Freescale Semiconductor