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— Data Path:
This block implements the bus master read/write datapath. It includes 16 bytes of register
storage and the necessary multiplex logic to support any required data alignment. The
internal read data bus is the primary input, and the internal write data bus is the primary
output.
The address and data path modules directly support the 2-stage pipelined internal bus. The
address path module represents the 1st stage of the bus pipeline (address phase), while the
data path module implements the 2nd stage of the pipeline (data phase).
— Program Model/Channel Arbitration:
This block implements the first section of the eDMA programming model as well as the
channel arbitration logic. The programming model registers are connected to the internal
peripheral bus (not shown). The eDMA peripheral request inputs and interrupt request
outputs are also connected to this block (via control logic).
— Control:
This block provides all the control functions for the eDMA engine. For data transfers where
the source and destination sizes are equal, the eDMA engine performs a series of source
read/destination write operations until the number of bytes specified in the minor loop byte
count has moved. For descriptors where the sizes are not equal, multiple accesses of the
smaller size data are required for each reference of the larger size. As an example, if the
source size references 16-bit data and the destination is 32-bit data, two reads are performed,
then one 32-bit write.
•
Transfer Control Descriptor Memory
— Memory Controller:
This logic implements the required dual-ported controller, managing accesses from the
eDMA engine as well as references from the internal peripheral bus. As noted earlier, in the
event of simultaneous accesses, the eDMA engine is given priority and the peripheral
transaction is stalled.
— Memory Array: TCD storage is implemented using a single-port, synchronous RAM array.
16.7.2
eDMA Basic Data Flow
The basic flow of a data transfer can be partitioned into three segments. As shown in
segment involves the channel activation. In the diagram, this example uses the assertion of the eDMA
peripheral request signal to request service for channel n. Channel activation via software and the
TCDn_CSR[START] bit follows the same basic flow as peripheral requests. The eDMA request input
signal is registered internally and then routed through the eDMA engine: first through the control module,
then into the program model and channel arbitration. In the next cycle, the channel arbitration performs,
using the fixed-priority or round-robin algorithm. After arbitration is complete, the activated channel
number is sent through the address path and converted into the required address to access the local memory
for TCDn. Next, the TCD memory is accessed and the required descriptor read from the local memory and
loaded into the eDMA engine address path channel x or y registers. The TCD memory is 64 bits wide to
minimize the time needed to fetch the activated channel descriptor and load it into the address path channel
x or y registers.
Freescale Semiconductor
MCF5329 Reference Manual, Rev 3
Enhanced Direct Memory Access (eDMA)
Figure
16-29, the first
16-25
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