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Universal Serial Bus Interface – On-The-Go Module
to draw more than the allocated amount of current, the USB host must disable the port and remove power.
USB VBUS is not provided on-chip. This processor provides pins for control and status to an external IC
capable of managing the VBUS downstream supply.
For OTG operations, external circuitry is required to manage the host negotiation protocol (HNP) and
session request protocol (SRP). External ICs that are capable of providing the OTG VBUS with support
for HNP and SRP, as well as support for programmable pullup and pulldown resistors on the USB DP and
DM lines are available from various manufacturers.
The on-chip FS/LS transceiver does not include USB DP and DM bias resistors. The primary function of
the transceiver is the physical signal conditioning of the external USB DP and DM cable signals for a
USB 2.0 network. Several USB system elements are not supported on the device as they are available via
standard products from various manufacturers.
21.1.2
Block Diagram
Figure 21-1
shows the USB On-The-Go interface using the on-chip full-speed/low-speed transceiver.
Figure 21-1. USB On-The-Go with on-chip FS/LS Transceiver Interface Block Diagram
Figure 21-2
illustrates the On-The-Go (OTG) configuration with an off-chip ULPI transceiver. The ULPI
transceiver is an implementation of the HS/FS/LS physical layer which encapsulates the 60+ pin UTMI+
interface using a 12-pin digital interface.
The board-level implementation of a ULPI based product is dependent on the PHY vendor. One possible
implementation is shown in
21-2
USB On-The-Go
Chip
Configuration
Module
Figure
21-1. The ULPI PHY manages USB clocking, DP/DM bias resistors,
MCF5329 Reference Manual, Rev 3
USBD_DP
FS/LS
USBD_DM
Transceiver
OTG
Control
Status
VBUS
Interrupt
SCL/SDA
I2C
Master
Freescale Semiconductor
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