Freescale Semiconductor MCF5329 Reference Manual page 323

After any channel requests service, a channel is selected for execution based on the arbitration and priority
levels written into the programmer's model. The eDMA engine read the entire TCD, including the TCD
control and status fields
the TCD is read, the first transfer is initiated on the internal bus unless a configuration error is detected.
Transfers from the source (as defined by the source address, TCDn_SADDR) to the destination (as defined
by the destination address, TCDn_DADDR) continue until the specified number of bytes
(TCDn_NBYTES) are transferred. When transfer is complete, the eDMA engine's local TCDn_SADDR,
TCDn_DADDR, and TCDn_CITER are written back to the main TCD memory and any minor loop
channel linking is performed, if enabled. If the major loop is exhausted, further post processing executes
(interrupts, major loop channel linking, and scatter/gather operations) if enabled.
TCDn_CSR
Field Name
START
ACTIVE
DONE
D_REQ
BWC
E_SG
INT_HALF
INT_MAJ
Table 16-32 shows how each DMA request initiates one minor-loop transfer (iteration) without CPU
intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA
preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration
count (BITER).
Freescale Semiconductor
(Table 16-31) for the selected channel into its internal address path module. As
Table 16-31. TCD Control and Status Fields
Control bit to start channel explicitly when using a software
initiated DMA service (Automatically cleared by hardware)
Status bit indicating the channel is currently in execution
Status bit indicating major loop completion (cleared by software
when using a software initiated DMA service)
Control bit to disable DMA request at end of major loop
completion when using a hardware initiated DMA service
Control bits for throttling bandwidth control of a channel
Control bit to enable scatter-gather feature
Control bit to enable interrupt when major loop is half complete
Control bit to enable interrupt when major loop completes
MCF5329 Reference Manual, Rev 3
Enhanced Direct Memory Access (eDMA)
Description
16-29