Freescale Semiconductor MCF5329 Reference Manual page 249

Address: 0xFC0A_4038 (PPDSDR_LCDCTLH)
7
R 0
W
Reset: 0
Figure 13-25. Port LCDCTLH Pin Data/Set Data Register (PPDSDR_LCDCTLH)
Field
PPDR_x Port x pin data bits.
(read) 0 Port x pin state is 0
1 Port x pin state is 1
PSDR_x Port x set data bits.
(write) 0 No effect.
1 Set corresponding PODR_x bit.
Note: See above figures for bit field positions.
13.3.4 Port Clear Output Data Registers (PCLRR_x)
Clearing a PCLRR_x register clears the corresponding bits in the PODR_x register. Setting it has no effect.
Reading the PCLRR_x register returns 0s. The PCLRR_x registers are each eight bits wide, but not all
ports use all eight bits. The register definitions for all ports are shown in the figures below.
Address: 0xFC0A_403F (PCLRR_BUSCTL)
0xFC0A_4040 (PCLRR_BE)
0xFC0A_4043 (PCLRR_FECI2C)
0xFC0A_4047 (PCLRR_TIMER)
7
R 0
W
Reset: 0
Figure 13-26. Port Clear Output Data Registers (PCLRR_x)
Freescale Semiconductor
6 5 4
0 0 0
0 0 0
Table 13-6. PPDSDR_x Field Descriptions
Description
6 5 4
0 0 0
0 0 0
MCF5329 Reference Manual, Rev 3
General Purpose I/O Module
Access: User read/write
3 2 1
0 0 0
0 0 0
Access: User write-only
3 2 1
0 0 0
PCLRR_x
0 0 0
0
PPDSDR_
LCDCTLH0
[PLCD
CTLH0]
0
0
0
13-21