Freescale Semiconductor MCF5329 Reference Manual page 530

Liquid Crystal Display Controller (LCDC)
Field
31 TFT display enable. Controls the format and timing of the output control signals. Active and passive displays use
TFT different signal timing formats as described in
controls the use of the frame rate control (FRC) in color mode. Refer to below table for TFT/COLOR setting
usage.
0 The LCD panel is a passive display.
1 The LCD panel is an active display: digital CRT signal format, FRC is bypassed.
30 Color display enable. Activates three channels of FRC in passive mode to allow use of the special 2 2/3 pixels
COLOR per output vector format. Refer to TFT bit field description for TFT/COLOR setting usage.
0 The LCD panel is a monochrome display.
1 The LCD panel is a color display.
29–28 Panel bus width. Specifies the panel bus width. Applicable for monochrome or passive matrix color monitors. For
PBSIZ passive color panels, only a 12-bit panel bus width is supported.
00 1-bit
01 Reserved
10 4-bit
11 8-bit
27–25 Indicates the number of bits per pixel in memory.
BPIX 000 1 bpp, FRC bypassed
001 2 bpp
010 4 bpp
011 8 bpp
100 12 bpp (16 bits of memory used)
101 16 bpp
110 18 bpp (32 bits of memory used)
111 Reserved
Note: To set normal 18 bpp mode, use the following settings: BPIX = 110, END_SEL = 0, SWAP_SEL = X (don't
care). To set Microsoft PAL_BGR 18 bpp mode, use the following: BPIX = 110, END_SEL = 1,
SWAP_SEL = 1.
24 Pixel polarity.
PIXPOL 0 Active high
1 Active low
23 First line marker polarity.
FLMPOL 0 Active high
1 Active low
22 Line pulse polarity.
LPPOL 0 Active high
1 Active low
22-10
Table 22-10. LCD_PCR Field Descriptions
Description
Section 22.4.9, "Panel Interface Signals and Timing."
TFT COLOR
0 0
0 1
1 0
1 1
MCF5329 Reference Manual, Rev 3
LCD Display
Monochrome
CSTN
Reserved
TFT
Freescale Semiconductor
TFT also